Advanced Interconnect and Packaging

Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottlenecks faced by modern integrated ci...

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Bibliographic Details
Main Author: Zhao, Wensheng
Format: eBook
Language:English
Published: Basel MDPI - Multidisciplinary Digital Publishing Institute 2023
Subjects:
N/a
Online Access:
Collection: Directory of Open Access Books - Collection details see MPG.ReNa
Description
Summary:Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottlenecks faced by modern integrated circuits. To resolve these interconnect problems, various emerging technologies, including airgap, nanocarbon, optical, and through-silicon via (TSV), have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to increase the integration density. More importantly, 3D integration and packaging also offer the most promising platform to implement "More-than-Moore" technologies, providing heterogeneous materials and technologies on a single chip. The "Advanced Interconnect and Packaging" Special Issue seeks to showcase research papers on new developments in advanced interconnect and packaging, i.e., on the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies. Additionally, there are two interesting papers on carbon nanotube interconnects and interconnect reliability issues.
Item Description:Creative Commons (cc), https://creativecommons.org/licenses/by/4.0/
Physical Description:1 electronic resource (266 p.)
ISBN:books978-3-0365-6732-7
9783036567334
9783036567327