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150702 ||| eng |
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|a 9781461413233
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| 100 |
1 |
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|a Saini, Sandeep
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| 245 |
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|a Low Power Interconnect Design
|h Elektronische Ressource
|c by Sandeep Saini
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| 250 |
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|a 1st ed. 2015
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| 260 |
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|a New York, NY
|b Springer New York
|c 2015, 2015
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| 300 |
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|a XVII, 152 p. 111 illus., 12 illus. in color
|b online resource
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| 505 |
0 |
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|a Part I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques
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| 653 |
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|a Processor Architectures
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Electronics and Microelectronics, Instrumentation
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| 653 |
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|a Microprocessors
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| 653 |
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|a Electronics
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| 653 |
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|a Circuits and Systems
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| 653 |
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|a Microelectronics
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| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b Springer
|a Springer eBooks 2005-
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| 856 |
4 |
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|u https://doi.org/10.1007/978-1-4614-1323-3?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 621.3815
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| 520 |
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|a This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques
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