VLSI Chip Design with the Hardware Description Language VERILOG An Introduction Based on a Large RISC Processor Design
This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on...
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| Format: | eBook |
| Language: | English |
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Berlin, Heidelberg
Springer Berlin Heidelberg
1996, 1996
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| Edition: | 1st ed. 1996 |
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| Online Access: | |
| Collection: | Springer Book Archives -2004 - Collection details see MPG.ReNa |
Table of Contents:
- Design of VLSI Circuits
- Design of VLSI Circuits
- RISC Architectures
- RISC Architectures
- Short Introduction to VERILOG
- Short Introduction to VERILOG
- External Specification of Behavior
- External Specification of Behavior
- Internal Specification of Coarse Structure
- Internal Specification of Coarse Structure
- Pipeline of the Coarse Structure Model
- Pipeline of the Coarse Structure Model
- Synthesis of Gate Model
- Synthesis of Gate Model
- Testing, Testability, Tester, and Testboard
- Testing, Testability, Tester, and Testboard
- Summary and Prospect
- Summary and Prospect
- HDL Models for Circuits and Architectures
- HDL Modeling with VERILOG.