VLSI Chip Design with the Hardware Description Language VERILOG An Introduction Based on a Large RISC Processor Design
This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on...
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| Format: | eBook |
| Language: | English |
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Berlin, Heidelberg
Springer Berlin Heidelberg
1996, 1996
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| Edition: | 1st ed. 1996 |
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| Online Access: | |
| Collection: | Springer Book Archives -2004 - Collection details see MPG.ReNa |
| Summary: | This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC. |
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| Physical Description: | XIV, 360 p. 37 illus online resource |
| ISBN: | 9783642610011 |