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140122 ||| eng |
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|a 9781475728965
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| 100 |
1 |
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|a Thomas, Donald E.
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| 245 |
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|a The Verilog® Hardware Description Language
|h Elektronische Ressource
|c by Donald E. Thomas, Philip R. Moorby
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| 250 |
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|a 4th ed. 1998
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| 260 |
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|a New York, NY
|b Springer US
|c 1998, 1998
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| 300 |
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|a XIX, 354 p
|b online resource
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| 505 |
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|a 1 Verilog — A Tutorial Introduction -- 2 Behavioral Modeling -- 3 Concurrent Processes -- 4 Logic Level Modeling -- 5 Advanced Timing -- 6 Logic Synthesis -- 7 Behavioral Synthesis -- 8 User-Defined Primitives -- 9 Switch Level Modeling -- 10 Projects -- Appendix A Tutorial Questions and Discussion -- Structural Descriptions -- Testbench Modules -- Combinational Circuits Using always -- Sequential Circuits -- Hierarchical Descriptions -- Finite State Machine and Datapath -- Cycle-Accurate Descriptions -- Appendix B Lexical Conventions -- White Space and Comments -- Operators -- Numbers -- Strings -- Identifiers, System Names, and Keywords -- Appendix C Verilog Operators -- Table of Operators -- Operator Precedence -- Operator Truth Tables -- Expression Bit Lengths -- Appendix D Verilog Gate Types -- Logic Gates -- BUF and NOT Gates -- BUFIF and NOTIF Gates -- MOS Gates -- Bidirectional Gates -- CMOS Gates -- Pullup and Pulldown Gates -- Appendix E Registers, Memories, Integers, and Time -- Registers -- Memories -- Integers and Times -- Appendix F System Tasks and Functions -- Display and Write Tasks -- Continuous Monitoring -- Strobed Monitoring -- File Output -- Simulation Time -- Stop and Finish -- Random -- Reading Data From Disk Files -- Appendix G Formal Syntax Definition -- Tutorial Guide to Formal Syntax Specification -- Source Text -- Declarations -- Primitive Instances -- Module Instantiation -- UDP Declaration and Instantiation -- Behavioral Statements -- Specify Section -- Expressions -- General
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| 653 |
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|a Computer-Aided Engineering (CAD, CAE) and Design
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| 653 |
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|a Electrical and Electronic Engineering
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| 653 |
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|a Electrical engineering
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| 653 |
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|a Computers
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| 653 |
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|a Computer Hardware
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Computer-aided engineering
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| 653 |
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|a Electronic Circuits and Systems
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| 700 |
1 |
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|a Moorby, Philip R.
|e [author]
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| 041 |
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7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 028 |
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|a 10.1007/978-1-4757-2896-5
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| 856 |
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|u https://doi.org/10.1007/978-1-4757-2896-5?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
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|a 621.3815
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| 520 |
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|a XV Acknowledgments xvii Chapter 1 Verilog - A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits II Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Behavioral Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines IS Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment("
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