Layout Minimization of CMOS Cells
The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer aided-design (CAD) programs are required to automate the...
| Main Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
New York, NY
Springer US
1992, 1992
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| Edition: | 1st ed. 1992 |
| Series: | The Springer International Series in Engineering and Computer Science
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| Subjects: | |
| Online Access: | |
| Collection: | Springer Book Archives -2004 - Collection details see MPG.ReNa |
Table of Contents:
- I. Introduction
- 1.1 Problem and Motivation
- 1.2 Layout Styles
- 1.3 Functional Cell Optimization
- 1.4 Proposed Approach
- II. Functional Cell Layout Methods
- 2.1 Functional Cell Design
- 2.2 Survey of Prior Methods
- 2.3 Critique of Prior Work
- III. Series-Parallel Cell Width Minimization
- 3.1 Graph Optimization Problems
- 3.2 Theory of Dual Trail Covering
- 3.3 Optimal Trail Covering without Reordering
- 3.4 Optimal Trail Covering with Reordering
- 3.5 Analysis of Complete Class of Practical Cells
- 3.6 Minimum-Width Rows of Cells
- IV. Planar Cell Width Minimization
- 4.1 Nonseries-Parallel Composition
- 4.2 P-TrailTrace Algorithm
- 4.3 Complete Study of Practical Planar Cells
- V. Single Cell Width and Height Minimization
- 5.1 Layout Problem
- 5.2 Extension of Series-Parallel Cell Theory
- 5.3 HR-TrailTrace Algorithm
- 5.4 Complete Study of Practical Cells
- 5.5 Planar Cell Layout
- VI. Cell Array Width and Height Minimization
- 6.1 Layout Problem
- 6.2 HRM-TrailTrace Algorithm
- 6.3 Experimental Results
- VII. Conclusions
- 7.1 Contributions
- 7.2 Practical Applications and Extensions