Hierarchical Modeling for VLSI Circuit Testing

by Bhattacharya, Debashis, Hayes, John P.
Published 1990

Layout Minimization of CMOS Cells

by Maziasz, Robert L., Hayes, John P.
Published 1992

Design, Analysis and Test of Logic Circuits Under Uncertainty

by Krishnaswamy, Smita, Markov, Igor L., Hayes, John P.
Published 2013

Quantum Circuit Simulation

by Viamontes, George F., Markov, Igor L., Hayes, John P.
Published 2009