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140122 ||| eng |
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|a 9781461526889
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| 100 |
1 |
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|a Lam, William K.C.
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| 245 |
0 |
0 |
|a Timed Boolean Functions
|h Elektronische Ressource
|b A Unified Formalism for Exact Timing Analysis
|c by William K.C. Lam, Robert K. Brayton
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| 250 |
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|a 1st ed. 1994
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| 260 |
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|a New York, NY
|b Springer US
|c 1994, 1994
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| 300 |
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|a XXI, 273 p
|b online resource
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| 505 |
0 |
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|a 1 Introduction -- 1.1 Overview -- 2 Preliminaries -- 2.1 Boolean Functions -- 2.2 Cubes and Covering -- 2.3 Binary Decision Diagrams -- 2.4 Boolean Networks and Circuits -- 2.5 Testing/Timing -- 3 Timed Boolean Functions -- 3.1 Introduction -- 3.2 Representation of Binary Signals -- 3.3 Modeling Timing Behaviors -- 3.4 Circuit Formulation -- 3.5 Event Properties -- 3.6 Representations Over Inputs -- 3.7 Decision Diagrams -- 3.8 ENF and TBF -- 3.9 Optimizations in Real and Boolean Domains -- 3.10 Summary -- 4 Exact Delay Computation -- 4.1 Introduction -- 4.2 Previous Work -- 4.3 Classification of Circuit Delay Models -- 4.4 Formulation for Exact Delay Computation -- 4.5 Solving the Boolean Linear Program -- 4.6 Exact 2-vector Delay -- 4.7 Exact Delay by Sequences of Vectors -- 4.8 Effects of Gate Delay Lower Bounds -- 4.9 Delay Computation Using TBF BDD’s -- 4.10 An Example: 4-bit Ripple Bypass Adder -- 4.11 Experimental Results -- 4.12 Minimum Delays -- 4.13 Exact Minimum Cycle Times for Sequential Circuits -- 4.14 Summary -- 5 Wavepipelining -- 5.1 Introduction -- 5.2 Wavepipelining of Combinational Circuits -- 5.3 Wavepipelining of Feedforward Sequential Circuits -- 5.4 Wavepipelining of Feedback Sequential Circuits -- 5.5 Analysis of General Wavepipelining -- 5.6 Manufacturing Precision: a New Dimension for Performance -- 5.7 Experimental Results -- 5.8 Summary -- 6 Exact Circuit Performance Validation -- 6.1 Introduction -- 6.2 Delay Fault Testing -- 6.3 Functional Delay Testing -- 6.4 Algebraic Relation Between RD sets and Dominated Paths -- 6.5 Robust Delay -- 6.6 Trade-off Between Performance Verifiability and Testing -- 6.7 Performance Verifiability, Probability of Error, and Testability -- 6.8 Experimental Results -- 6.9 Exact Verifiable Delay Analysis -- 6.10 Specification Directed Boolean Synthesis forComplete Per-formance Verifiability -- 6.11 Summary -- 7 Conclusions -- 7.1 Comparing TBF Approach with Other Competitive Methods
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| 653 |
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|a Electrical and Electronic Engineering
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| 653 |
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|a Electrical engineering
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Electronic Circuits and Systems
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| 700 |
1 |
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|a Brayton, Robert K.
|e [author]
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| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 490 |
0 |
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|a The Springer International Series in Engineering and Computer Science
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| 028 |
5 |
0 |
|a 10.1007/978-1-4615-2688-9
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| 856 |
4 |
0 |
|u https://doi.org/10.1007/978-1-4615-2688-9?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 621.3815
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| 520 |
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|a Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing
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