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Hierarchical Modeling for VLSI Circuit Testing

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recogni...

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Bibliographic Details
Main Authors: Bhattacharya, Debashis, Hayes, John P. (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 1990, 1990
Edition:1st ed. 1990
Series:The Springer International Series in Engineering and Computer Science
Subjects:
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Computer-aided Engineering
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1 Introduction
  • 1.1 Background
  • 1.2 Prior Work
  • 1.3 Outline
  • 2 Circuit and Fault Modeling
  • 2.1 Vector Sequence Notation
  • 2.2 Circuit and Fault Models
  • 2.3 Case Study: k-Regular Circuits
  • 3 Hierarchical Test Generation
  • 3.1 Vector Cubes
  • 3.2 Test Generation
  • 3.3 Implementation and Experimental Results
  • 4 Design for Testability
  • 4.1 Ad Hoc Techniques
  • 4.2 Level Separation (LS) Method
  • 4.3 Case Study: ALU
  • 5 Concluding Remarks
  • 5.1 Summary
  • 5.2 Future Directions
  • Appendix A: Proofs of Theorems
  • A.1 Proof of Theorem 3.2
  • A.2 Proof of Theorem 3.3
  • A.3 Proof of Theorem 4.1

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