The Verilog® Hardware Description Language
xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural...
| Main Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
New York, NY
Springer US
2002, 2002
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| Edition: | 5th ed. 2002 |
| Subjects: | |
| Online Access: | |
| Collection: | Springer Book Archives -2004 - Collection details see MPG.ReNa |
Table of Contents:
- Verilog — A Tutorial Introduction
- Logic Synthesis
- Behavioral Modeling
- Concurrent Processes
- Module Hierarchy
- Logic Level Modeling
- Cycle-Accurate Specification
- Advanced Timing
- User-Defined Primitives
- Switch Level Modeling
- Projects