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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge res...

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Bibliographic Details
Main Authors: Noia, Brandon, Chakrabarty, Krishnendu (Author)
Format: eBook
Language:English
Published: Cham Springer International Publishing 2014, 2014
Edition:1st ed. 2014
Subjects:
Semiconductors
Electronic Circuits
Processor Architectures
Microprocessors
Electronic Circuits And Systems
Computer Architecture
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • Introduction
  • Wafer Stacking and 3D Memory Test
  • Built-in Self-Test for TSVs
  • Pre-Bond TSV Test Through TSV Probing
  • Pre-Bond TSV Test Through TSV Probing
  • Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths
  • Post-Bond Test Wrappers and Emerging Test Standards
  • Test-Architecture Optimization and Test Scheduling
  • Conclusions

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