Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptabl...
| Main Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
New York, NY
Springer US
2007, 2007
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| Edition: | 2nd ed. 2007 |
| Series: | Frontiers in Electronic Testing
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| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
Table of Contents:
- Functional and Parametric Defect Models
- Digital CMOS Fault Modeling
- Defects in Logic Circuits and their Test Implications
- Testing Defects and Parametric Variations in RAMs
- Defect-Oriented Analog Testing
- Yield Engineering
- Conclusion