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231010 ||| eng |
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|a 9783031382307
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| 100 |
1 |
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|a Jain, Vikram
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| 245 |
0 |
0 |
|a Towards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning
|h Elektronische Ressource
|b Journey from Single-core Acceleration to Multi-core Heterogeneous Systems
|c by Vikram Jain, Marian Verhelst
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| 250 |
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|a 1st ed. 2024
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| 260 |
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|a Cham
|b Springer Nature Switzerland
|c 2024, 2024
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| 300 |
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|a XXIII, 186 p. 93 illus., 83 illus. in color
|b online resource
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| 505 |
0 |
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|a Chapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion
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| 653 |
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|a Machine learning
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| 653 |
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|a Embedded Systems
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| 653 |
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|a Embedded computer systems
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| 653 |
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|a Machine Learning
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Processor Architectures
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| 653 |
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|a Microprocessors
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| 653 |
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|a Electronic Circuits and Systems
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| 653 |
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|a Computer architecture
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| 700 |
1 |
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|a Verhelst, Marian
|e [author]
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| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b Springer
|a Springer eBooks 2005-
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| 028 |
5 |
0 |
|a 10.1007/978-3-031-38230-7
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| 856 |
4 |
0 |
|u https://doi.org/10.1007/978-3-031-38230-7?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 6,213,815
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| 520 |
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|a This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations. Discusses the need for scaling to multi-core systems for machine learning and several architectural and software optimizations; Covers single-core, homogeneous and heterogeneous multi-core Systems-on-chip for machine learning applications; Discusses the benefits of heterogeneity in the context of machine learning.
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