Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures
This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of...
| Main Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
Cham
Springer International Publishing
2020, 2020
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| Edition: | 1st ed. 2020 |
| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
Table of Contents:
- Introduction to Network-on-Chip Designs and Tests
- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems
- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems
- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems
- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems
- Temperature-aware design strategy for 3D-NoC-based multicore systems
- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems