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Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...

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Bibliographic Details
Main Author: Taraate, Vaibbhav
Format: eBook
Language:English
Published: Singapore Springer Nature Singapore 2019, 2019
Edition:1st ed. 2019
Subjects:
Microprogramming 
Control Structures And Microprogramming
Electronic Circuits
Logic Design
Electronic Circuits And Systems
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • Introduction
  • SOC Design
  • RTL Design Guidelines
  • RTL Design and Verification
  • Processor cores and Architecture design
  • Buses and protocols in SOC designs
  • DSP Algorithms and Video Processing
  • ASIC and FPGA Synthesis
  • Static Timing Analysis
  • SOC Prototyping
  • SOC Prototyping guidelines
  • Design Integration and SOC synthesis
  • Interconnect delays and Timing
  • SOC Prototyping and debug techniques
  • Testing at the board level

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