A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...
| Main Authors: | , , |
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| Format: | eBook |
| Language: | English |
| Published: |
Cham
Springer International Publishing
2014, 2014
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| Edition: | 1st ed. 2014 |
| Series: | Theoretical Computer Science and General Issues
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| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
| Summary: | This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work |
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| Physical Description: | XII, 352 p. 147 illus online resource |
| ISBN: | 9783319139067 |