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140122 ||| eng |
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|a 9783642559891
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| 100 |
1 |
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|a Cortadella, J.
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| 245 |
0 |
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|a Logic Synthesis for Asynchronous Controllers and Interfaces
|h Elektronische Ressource
|c by J. Cortadella, M. Kishinevsky, A. Kondratyev, Luciano Lavagno, Alex Yakovlev
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| 250 |
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|a 1st ed. 2002
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| 260 |
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|a Berlin, Heidelberg
|b Springer Berlin Heidelberg
|c 2002, 2002
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| 300 |
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|a XIII, 273 p
|b online resource
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| 505 |
0 |
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|a 8.5 Other Examples -- 9. Other Work -- 9.1 Hardware Description Languages -- 9.2 Structural and Unfolding-based Synthesis -- 9.3 Direct Mapping of STGs into Asynchronous Circuits -- 9.4 Datapath Design and Interfaces -- 9.5 Test Pattern Generation and Design for Testability -- 9.6 Verification -- 9.7 Asynchronous Silicon -- 10. Conclusions -- References
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| 505 |
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|a 1. Introduction -- 1.1 A Little History -- 1.2 Advantages of Asynchronous Logic -- 1.3 Asynchronous Control Circuits -- 2. Design Flow -- 2.1 Specification of Asynchronous Controllers -- 2.2 Transition Systems and State Graphs -- 2.3 Deriving Logic Equations -- 2.4 State Encoding -- 2.5 Logic Decomposition and Technology Mapping -- 2.6 Synthesis with Relative Timing -- 2.7 Summary -- 3. Background -- 3.1 Petri Nets -- 3.2 Structural Theory of Petri Nets -- 3.3 Calculating the Reachability Graph of a Petri Net -- 3.4 Transition Systems -- 3.5 Deriving Petri Nets from Transition Systems -- 3.6 Algorithm for Petri Net Synthesis -- 3.7 Event Insertion in Transition Systems -- 4. Logic Synthesis -- 4.1 Signal Transition Graphs and State Graphs -- 4.2 Implement ability as a Logic Circuit -- 4.3 Boolean Functions -- 4.4 Gate Netlists -- 4.5 Deriving a Gate Net list -- 4.6 What is Speed-Independence? -- 4.7 Summary -- 5. State Encoding -- 5.1 Methods for Complete State Coding --
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| 505 |
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|a 5.2 Constrained Signal Transition Event Insertion -- 5.3 Selecting SIP-Sets -- 5.4 Transformation of State Graphs -- 5.5 Completeness of the Method -- 5.6 An Heuristic Strategy to Solve CSC -- 5.7 Cost Function -- 5.8 Related Work -- 5.9 Summary -- 6. Logic Decomposition -- 6.1 Overview -- 6.2 Architecture-Based Decomposition -- 6.3 Logic Decomposition Using Algebraic Factorization -- 6.4 Logic Decomposition Using Boolean Relations -- 6.5 Experimental Results -- 6.6 Summary -- 7. Synthesis with Relative Timing -- 7.1 Motivation -- 7.2 Lazy Transition Systems and Lazy State Graphs -- 7.3 Overview and Example -- 7.4 Timing Assumptions -- 7.5 Synthesis with Relative Timing -- 7.6 Automatic Generation of Timing Assumptions -- 7.7 Back-Annotation of Timing Constraints -- 7.8 Experimental Results -- 7.9 Summary -- 8. Design Examples -- 8.1 Handshake Communication -- 8.2 VME Bus Controller -- 8.3 Controller for Self-timed A/D Converter -- 8.4 “Lazy” Token Ring Adapter --
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| 653 |
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|a Computer Communication Networks
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| 653 |
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|a Electronics and Microelectronics, Instrumentation
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| 653 |
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|a Computer networks
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| 653 |
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|a Optical Materials
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| 653 |
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|a Logic design
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| 653 |
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|a Logic Design
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| 653 |
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|a Electronics
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| 653 |
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|a Optical materials
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| 700 |
1 |
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|a Kishinevsky, M.
|e [author]
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| 700 |
1 |
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|a Kondratyev, A.
|e [author]
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| 700 |
1 |
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|a Lavagno, Luciano
|e [author]
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| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 490 |
0 |
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|a Springer Series in Advanced Microelectronics
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| 028 |
5 |
0 |
|a 10.1007/978-3-642-55989-1
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| 856 |
4 |
0 |
|u https://doi.org/10.1007/978-3-642-55989-1?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 621.381
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| 520 |
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|a This book is devoted to logic synthesis and design techniques for asynchronous circuits. It uses the mathematical theory of Petri Nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool. Asynchronous circuits have so far been designed mostly by hand, and are thus much less common than their synchronous counterparts, which have enjoyed a high level of design automation since the mid-1970s. Asynchronous circuits, on the other hand, can be very useful to tackle clock distribution, modularity, power dissipation and electro-magnetic interference in digital integrated circuits. This book provides the foundation needed for CAD-assisted design of such circuits, and can also be used as the basis for a graduate course on logic design
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