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140122 ||| eng |
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|a 9781475767155
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100 |
1 |
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|a IBBETT.
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245 |
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|a The Architecture of High Performance Computers
|h Elektronische Ressource
|c by IBBETT.
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250 |
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|a 1st ed. 1982
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260 |
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|a New York, NY
|b Springer New York
|c 1982, 1982
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300 |
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|a VII, 172 p
|b online resource
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505 |
0 |
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|a 1 Introduction -- 2 Instructions and Addresses -- 3 Storage Hierarchies -- 4 Pipelines -- 5 Instruction Buffering -- 6 Parallel Functional Units -- 7 Vector Processors -- References
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653 |
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|a Computers
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653 |
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|a Computer Hardware
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041 |
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7 |
|a eng
|2 ISO 639-2
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989 |
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|b SBA
|a Springer Book Archives -2004
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028 |
5 |
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|a 10.1007/978-1-4757-6715-5
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856 |
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|u https://doi.org/10.1007/978-1-4757-6715-5?nosfx=y
|x Verlag
|3 Volltext
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082 |
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|a 004
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520 |
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|a Introduction 1. 1 Historical Developments 1 1. 2 Techniques for Improving Performance 2 1. 3 An Architectural Design Example 3 2 Instructions and Addresses 2. 1 Three-address Systems - The CDC 6600 and 7600 7 2. 2 Two-address Systems - The IBM System/360 and /370 10 2. 3 One-address Systems 12 2. 4 Zero-address Systems 15 2. 5 The MU5 Instruction Set 17 2. 6 Comparing Instruction Formats 22 3 Storage Hierarcbies 3. 1 Store Interleaving 26 3. 2 The Atlas Paging System 29 3. 3 IBM Cache Systems 33 3. 4 The MU5 Name Store 37 3. 5 Data Transfers in the MU5 Storage Hierarchy 44 4 Pipelines 4. 1 The MU5 Primary Operand Unit Pipeline 49 4. 2 Arithmetic Pipelines - The TI ASC 62 4. 3 The IBM System/360 Model 91 Common Data Bus 67 5 Instruction Buffering 5. 1 The IBM System/360 Model 195 Instruction Processor 72 5. 2 Instruction Buffering in CDC Computers 77 5. 3 The MU5 Instruction Buffer Unit 82 5. 4 The CRAY-1 Instruction Buffers 87 5. 5 Position of the Control Point 89 6 Parallel Functional Units 6. 1 The CDC 6600 Central Processor 95 6. 2 The CDC 7600 Central Processor 104 6. 3 Performance 110 6 • 4 The CRA Y-1 112 7 Vector Processors 7. 1 Vector Facilities in MU5 126 7. 2 String Operations in MU5 136 7. 3 The CDC Star-100 142 7. 4 The CDC CYBER 205 146 7
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