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140122 ||| eng |
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|a 9781475734157
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| 100 |
1 |
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|a Bing Lu
|e [editor]
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| 245 |
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|a Layout Optimization in VLSI Design
|h Elektronische Ressource
|c edited by Bing Lu, Ding-Zhu Du, S. Sapatnekar
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| 250 |
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|a 1st ed. 2001
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| 260 |
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|a New York, NY
|b Springer US
|c 2001, 2001
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| 300 |
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|a VIII, 288 p
|b online resource
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| 505 |
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|a 1. Integrated Floorplanning and Interconnect Planning -- 2. Interconnect Planning -- 3. Modern Standard-cell Placement Techniques -- 4. Non-Hanan Optimization for Global VLSI Interconnect -- 5. Techniques for Timing-Driven Routing -- 6. Interconnect Modeling and Design with Consideration of Inductance -- 7. Modeling and Characterization of IC Interconnects and Packagings for the Signal Intergrity Verification on High-Performance VLSI Circuits -- 8. Tradeoffs in Digital Binary Adder Design: the Effects of Floorplanning, Number of Levels of Metals, and Supply Voltage on Performance and Area
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| 653 |
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|a Computer science
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| 653 |
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|a Computer-Aided Engineering (CAD, CAE) and Design
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| 653 |
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|a Computer simulation
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| 653 |
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|a Electrical and Electronic Engineering
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| 653 |
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|a Electrical engineering
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| 653 |
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|a Computer Modelling
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|a Electronic circuits
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|a Computer-aided engineering
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|a Applications of Mathematics
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|a Electronic Circuits and Systems
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| 653 |
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|a Theory of Computation
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| 653 |
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|a Mathematics
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| 700 |
1 |
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|a Ding-Zhu Du
|e [editor]
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| 700 |
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|a Sapatnekar, S.
|e [editor]
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| 041 |
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7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 490 |
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|a Network Theory and Applications
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| 028 |
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|a 10.1007/978-1-4757-3415-7
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| 856 |
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|u https://doi.org/10.1007/978-1-4757-3415-7?nosfx=y
|x Verlag
|3 Volltext
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|a 003.3
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| 520 |
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|a Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre sented in Chapter 1. To reduce the run time, different interconnect plan ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques
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