Cover Image
Read Now

VLSI — Compatible Implementations for Artificial Neural Networks

This book introduces several state-of-the-art VLSI implementations of artificial neural networks (ANNs). It reviews various hardware approaches to ANN implementations: analog, digital and pulse-coded. The analog approach is emphasized as the main one taken in the later chapters of the book. The area...

Full description

Bibliographic Details
Main Authors: Fakhraie, Sied Mehdi, Smith, Kenneth C. (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 1997, 1997
Edition:1st ed. 1997
Series:The Springer International Series in Engineering and Computer Science
Subjects:
Complex Systems
Electrical And Electronic Engineering
Electrical Engineering
Electronic Circuits
System Theory
Mathematical Physics
Electronic Circuits And Systems
Theoretical, Mathematical And Computational Physics
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 4.6 Performance of Simple SyMOS Networks
  • 4.7 Architecture Design in Neural-Network Hardware
  • 4.8 The Resource-Finding Exploration
  • 4.9 The Current-Source-Inhibited Architecture (CSIA)
  • 4.10 The Switchable-Sign-Synapse Architecture (SSSA)
  • 4.11 Digital-Analog Switchable-Sign-Synapse Architecture (DASA)
  • 4.12 Simulation Results and Comparison
  • 4.13 Our Choice of the Way to Go
  • 4.14 Summary
  • 5 Design, Modeling, and Implementation of a Synapse-MOS Device
  • 5.1 Introduction
  • 5.2 Design of a SyMOS Device in a CMOS Technology
  • 5.3 Implementation
  • 5.4 Reliability Issues
  • 5.5 Summary
  • 6 Synapse-MOS Artificial Neural Networks (SANNs)
  • 6.1 Introduction
  • 6.2 Overview of the Work Leading to Hardware Implementation
  • 6.3 Guidelines for Neural-Network Hardware Design
  • 6.4 Design and VLSI Implementation
  • 6.5 Structure of an SSSA Chip.-6.6 Training Algorithm
  • 6.7 Experimental Results
  • 6.8 Summary
  • 7 Analog Quadratic Neural Networks (AQNNs)
  • 7.1 Introduction
  • 7.2 Background
  • 7.3 Design of an “Analog Quadratic Neural Network (AQNN)”
  • 7.4 Training
  • 7.5 VLSI Implementation
  • 7.6 Test Results
  • 7.7 Applications
  • 7.8 Summary and Future Work
  • 8 Conclusion and Recommendations for Future Work
  • 8.1 Summary of the Work
  • 8.2 Contributions of this work
  • 8.3 Recommendations for Future Work
  • Appendix A Review of Nonvolatile Semiconductor Memory Devices
  • A.1 Background
  • A.2 Device Review
  • A.2.1 Charge-Trapping Devices
  • A.2.2 Floating-Gate Devices
  • A.3 Conclusion
  • Appendix B Scaling Effects
  • B.1 The Effect of the Scaling of CMOS Technology on SANNs
  • Appendix C Performance Evaluation
  • C.1 Speed
  • C.2 Power Consumption
  • C.2.1 Detailed Calculation of Power Dissipation
  • C.3 Area
  • C.4 Overall Performance
  • References
  • 1 Introduction and Motivation
  • 1.1 Introduction
  • 1.2 Motivation
  • 1.3 Objectives of this Work
  • 1.4 Organization of the Book
  • 2 Review of Hardware-Implementation Techniques
  • 2.1 Introduction
  • 2.2 Taxonomies of Neural Hardware
  • 2.3 Pulse-Coded Implementations
  • 2.4 Digital Implementations
  • 2.5 Analog Implementations
  • 2.6 Comparison of Some Existing Systems
  • 2.7 Summary
  • 3 Generalized Artificial Neural Networks (GANNs)
  • 3.1 Introduction
  • 3.2 Generalized Artificial Neural Networks (GANNs)
  • 3.3 Nonlinear MOS-Compatible Semi-Quadratic Synapses
  • 3.4 Networks Composed of Semi-Quadratic Synapses
  • 3.5 Training Equations
  • 3.6 Simulation and Verification of the Approach
  • 3.7 Summary
  • 4 Foundations: Architecture Design
  • 4.1 Introduction
  • 4.2 Feedforward Networks with Linear Synapses
  • 4.3 Feedforward Networks with Quadratic Synapses
  • 4.4 Single-Transistor-Synapse Feedforward Networks
  • 4.5 Intelligent MOS Transistors: SyMOS

Similar Items