Formal Equivalence Checking and Design Debugging
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to...
| Main Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
New York, NY
Springer US
1998, 1998
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| Edition: | 1st ed. 1998 |
| Series: | Frontiers in Electronic Testing
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| Subjects: | |
| Online Access: | |
| Collection: | Springer Book Archives -2004 - Collection details see MPG.ReNa |
Table of Contents:
- 1 Introduction
- 1.1 Problems of Interest
- 1.2 Organization
- I Equivalence Checking
- 2 Symbolic Verification
- 3 Incremental Verification for Combinational Circuits
- 4 Incremental Verification for Sequential Circuits
- 5 AQUILA: A Local BDD-based Equivalence Verifier
- 6 Algorithm for Verifying Retimed Circuits
- 7 RTL-to-Gate Verification 123
- II Logic Debugging
- 8 Introduction to Logic Debugging
- 9 ErrorTracer: Error Diagnosis by Fault Simulation
- 10 Extension to Sequential Error Diagnosis
- 11 Incremental Logic Rectification