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140122 ||| eng |
| 020 |
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|a 9781461536369
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| 100 |
1 |
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|a Gajski, Daniel D.
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| 245 |
0 |
0 |
|a High — Level Synthesis
|h Elektronische Ressource
|b Introduction to Chip and System Design
|c by Daniel D. Gajski, Nikil D. Dutt, Allen C-H Wu, Steve Y-L Lin
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| 250 |
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|a 1st ed. 1992
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| 260 |
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|a New York, NY
|b Springer US
|c 1992, 1992
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| 300 |
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|a XV, 359 p
|b online resource
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| 505 |
0 |
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|a 4.4 Hardware-Specific HDL Features -- 4.5 HDL Formats -- 4.6 A Discussion of Some HDLs -- 4.7 Matching Languages to Target Architectures -- 4.8 Modeling Guidelines for HDLs -- 4.9 Summary and Future Directions -- 4.10 Exercises -- 5 Design Representation and Transformations -- 5.1 Introduction -- 5.2 Design Flow in High-Level Synthesis: An Example -- 5.3 HDL Compilation -- 5.4 Representation of HDL Behavior -- 5.5 Representation of HLS Outputs -- 5.6 Design Views and Complete Representation Schemes for High- Level Synthesis -- 5.7 Transformations -- 5.8 Summary and Future Directions -- 5.9 Exercises -- 6 Partitioning -- 6.1 Introduction -- 6.2 Basic Partitioning Methods -- 6.3 Partitioning in High-Level Synthesis -- 6.4 Summary and Future Directions -- 6.5 Exercises -- 7 Scheduling -- 7.1 Problem Definition -- 7.2 Basic Scheduling Algorithms -- 7.3 Scheduling with Relaxed Assumptions -- 7.4 Other Scheduling Formulations -- 7.5 Summary and Future Directions -- 7.6 Exercises --
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| 505 |
0 |
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|a 1 Introduction -- 1.1 The Need for Design Automation on Higher Abstraction Levels -- 1.2 Levels of Abstraction -- 1.3 Definition of Synthesis -- 1.4 Languages, Designs and Technologies -- 1.5 Essential Issues in Synthesis -- 1.6 Status and Future of High-Level Synthesis -- 1.7 Summary -- 1.8 Exercises -- 2 Architectural Models in Synthesis -- 2.1 Design Styles and Target Architectures -- 2.2 Combinatorial Logic -- 2.3 Finite State Machines -- 2.4 Finite State Machine with a Datapath -- 2.5 System Architecture -- 2.6 Engineering Considerations -- 2.7 Summary and Future Directions -- 2.8 Exercises -- 3 Quality Measures -- 3.1 Introduction -- 3.2 The Relationship between Structural and Physical Designs -- 3.3 Area Measures -- 3.4 Performance Measures -- 3.5 Other Measures -- 3.6 Summary and Future Directions -- 3.7 Exercises -- 4 Design Description Languages -- 4.1 Introduction to HDLs -- 4.2 Language Models vs. Architectural Styles -- 4.3 Programming Language Features for HDLs --
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| 505 |
0 |
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|a 8 Allocation -- 8.1 Problem Definition -- 8.2 Datapath Architectures -- 8.3 Allocation Tasks -- 8.4 Greedy Constructive Approaches -- 8.5 Decomposition Approaches -- 8.6 Iterative Refinement Approach -- 8.7 Summary and Future Directions -- 8.8 Exercises -- 9 Design Methodology for High-Level Synthesis -- 9.1 Basic Concepts in Design Methodology -- 9.2 Generic Synthesis System -- 9.3 System Synthesis -- 9.4 Chip Synthesis -- 9.5 Logic and Sequential Synthesis -- 9.6 Physical-Design Methodology -- 9.7 System Database -- 9.8 Component Database -- 9.9 Conceptualization environment -- 9.10 Summary and Further Research -- 9.11 Exercises
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| 653 |
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|a Computer-Aided Engineering (CAD, CAE) and Design
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| 653 |
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|a Electrical and Electronic Engineering
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| 653 |
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|a Electrical engineering
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Computer-aided engineering
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| 653 |
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|a Electronic Circuits and Systems
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| 700 |
1 |
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|a Dutt, Nikil D.
|e [author]
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| 700 |
1 |
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|a Wu, Allen C-H.
|e [author]
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| 700 |
1 |
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|a Lin, Steve Y-L.
|e [author]
|
| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
|
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|b SBA
|a Springer Book Archives -2004
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| 028 |
5 |
0 |
|a 10.1007/978-1-4615-3636-9
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| 856 |
4 |
0 |
|u https://doi.org/10.1007/978-1-4615-3636-9?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 621.3815
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| 520 |
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|a Research on high-level synthesis started over twenty years ago, but lower-level tools were not available to seriously support the insertion of high-level synthesis into the mainstream design methodology. Since then, substantial progress has been made in formulating and understanding the basic concepts in high-level synthesis. Although many open problems remain, high-level synthesis has matured. High-Level Synthesis: Introduction to Chip and System Design presents a summary of the basic concepts and results and defines the remaining open problems. This is the first textbook on high-level synthesis and includes the basic concepts, the main algorithms used in high-level synthesis and a discussion of the requirements and essential issues for high-level synthesis systems and environments. A reference text like this will allow the high-level synthesis community to grow and prosper in the future
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