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VHDL Designer’s Reference

too vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to log...

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Bibliographic Details
Main Authors: Bergé, Jean-Michel, Fonkoua, Alain (Author), Maginot, Serge (Author), Rouillard, Jacques (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 1992, 1992
Edition:1st ed. 1992
Subjects:
Electrical And Electronic Engineering
Electrical Engineering
Computers
Computer Hardware
Electronic Circuits
Electronic Circuits And Systems
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1. Introduction
  • 1.1. VHDL Status
  • 1.2. The VHDL Spectrum
  • 1.3. Models, Modeling, and Modelware
  • 1.4. The Other Languages and Formats
  • 2. VHDL Tools
  • 2.1. Introduction
  • 2.2. Evaluating VHDL tools
  • 2.3. Technology of Platforms
  • 3. VHDL and Modeling Issues
  • 3.1. Introduction
  • 3.2. Core VHDL Concepts
  • 3.3. Abstraction
  • 3.4. Hierarchy
  • 3.5. Modularity
  • 3.6. Reusability
  • 3.7. Portability
  • 3.8. Efficiency
  • 3.9. Documentation
  • 3.10. Synthesis
  • 3.11. Conclusion
  • 4. Structuring the Environment
  • 4.1. Choosing a Logic System
  • 4.2. Utility Packages
  • 5. System Modeling
  • 5.1. Introduction
  • 5.2. The FSM with a Single Thread of Control
  • 5.3. Multiple Threads of Control
  • 5.4. Hierarchy: State Charts and S-Nets
  • 5.5. Conclusion
  • 6. Structuring Methodology
  • 6.1. Structuring
  • 6.2. What are the Possibilities of VHDL?
  • 6.3. To Summarize
  • 7. Tricks and Traps
  • 7.1. Modeling Traps
  • 7.2. Modeling Tricks
  • 7.3. Pitfalls
  • 7.4. Designer
  • 8. M and VHDL
  • 8.1. Introduction
  • 8.2. Design Unit
  • 8.3. Sequential and Concurrent Domains
  • 8.4. Objects
  • 8.5. Predefined Operators
  • 8.6. Statements
  • 8.7. Description Level
  • 8.8. Translating from M to VHDL
  • 8.9. Conclusion
  • 9. Verilog and VHDL
  • 9.1. Introduction
  • 9.2. Design Unit
  • 9.3. Sequential and Concurrent Domains
  • 9.4. Objects
  • 9.5. Predefined Operators
  • 9.6. Statements
  • 9.7. Description Level
  • 9.8. Translating from Verilog to VHDL
  • 9.9. Conclusion
  • 10. UDL/I and VHDL
  • 10.1. Introduction
  • 10.2. Design Unit
  • 10.3. Sequential and Concurrent Domains
  • 10.4. Objects
  • 10.5. UDL/I Structural Description
  • 10.6. UDL/I Behavioral Description
  • 10.7. UDL/I Assertion Section
  • 10.8. Description Level
  • 10.9. Translating from UDL/I to VHDL
  • 10.10. Conclusion
  • 11. Memo
  • 12. Index

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