Cover Image
Read Now

High-Level System Modeling Specification Languages

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network protocols, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent...

Full description

Bibliographic Details
Other Authors: Bergé, Jean-Michel (Editor), Levia, Oz (Editor), Rouillard, Jacques (Editor)
Format: eBook
Language:English
Published: New York, NY Springer US 1995, 1995
Edition:1st ed. 1995
Series:Current Issues in Electronic Modeling
Subjects:
Engineering
Computer Science
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Computers
Computer Hardware
Electronic Circuits
Computer-aided Engineering
Electronic Circuits And Systems
Theory Of Computation
Technology And Engineering
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1. Specification-Modeling Methodologies for Reactive-System Design
  • 1.1. Introduction
  • 1.2. Characteristics of Reactive Systems
  • 1.3. Specification-Modeling Methodology Requirements
  • 1.4. Specification-Modeling Methodology for Reactive Systems
  • 1.5. A Survey of Methodologies
  • 1.6. Summary
  • 1.7. Recommendations
  • 1.8. Conclusions
  • 2. Survey on Languages for Object Oriented Hardware Design Methodologies
  • 2.1. Introduction
  • 2.2. Introduction to Object-Oriented Design
  • 2.3. Possible Approaches
  • 3. VSPEC: A Declarative Requirements Specification Language for VHDL
  • 3.1. Introduction
  • 3.2. Important VHDL Constructs
  • 3.3. The VSPEC Clauses
  • 3.4. Formal Representation of VSPEC
  • 3.5. Extended Example: 16-bit Move Machine
  • 3.6. Related Work
  • 3.7. Current Status and Future Directions
  • 4. Communication Protocols Implemented in Hardware: VHDL Generation from Estelle
  • 4.1. Introduction
  • 4.2. VHDL versus Estelle Semantics
  • 4.3. Estelle to VHDL Translation Model
  • 4.4. Conclusions
  • 5. An Algorithm for the Translation of SDL into Synthesizable VHDL
  • 5.1. Introduction
  • 5.2. The SDL Subset
  • 5.3. Synthesis Constraints
  • 5.4. The Mapping Algorithm
  • 5.5. Structure
  • 5.6. Data Definition
  • 5.7. Process Communication
  • 5.8. Process Behaviour
  • 5.9. Variable Declaration
  • 5.10. Example of Implementation
  • 5.11. Conclusion
  • 6. From LOTOS to VHDL
  • 6.1. Introduction
  • 6.2. Languages
  • 6.3. Translation
  • 6.4. Conclusion
  • 6.5. Appendix: A Complete Example
  • 7. Using an X-Machine to Model a Video Cassette Recorder
  • 7.1. Introduction
  • 7.2. The Basic Model
  • 7.3. Extending the Machine to handle Fast-forward and Rewind Operations
  • 7.4. Programming the VCR
  • 7.5. Combining the Parts of the Model
  • 7.6. Adding a Model of the Video Tape
  • 7.7. Animation and Execution of theSpecification
  • 7.8. Verification Issues
  • 7.9. Evaluation and Conclusion

Similar Items