Verilog — 2001 A Guide to the New Features of the Verilog® Hardware Description Language
by Phil Moorby The Verilog Hardware Description Language has had an amazing impact on the mod em electronics industry, considering that the essential composition of the language was developed in a surprisingly short period of time, early in 1984. Since its introduc tion, Verilog has changed very l...
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| Format: | eBook |
| Language: | English |
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New York, NY
Springer US
2002, 2002
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| Edition: | 1st ed. 2002 |
| Series: | The Springer International Series in Engineering and Computer Science
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| Subjects: | |
| Online Access: | |
| Collection: | Springer Book Archives -2004 - Collection details see MPG.ReNa |
Table of Contents:
- 1. Combined port and data type declarations
- 2. ANSI C style module declarations
- 3. Module port parameter lists
- 4. ANSI C style UDP declarations
- 5. Variable initial value at declaration
- 6. ANSI C style task/function declarations
- 7. Automatic (re-entrant) tasks
- 8. Automatic (recursive) functions
- 9. Constant functions
- 10. Comma separated sensitivity lists
- 11. Combinational logic sensitivity lists
- 12. Implicit nets for continuous assignments
- 13. Disabling implicit net declarations
- 14. Variable vector part selects
- 15. Multidimensional arrays
- 16. Arrays of net and real data types
- 17. Array bit and part selects
- 18. Signed reg, net and port declarations
- 19. Signed based integer numbers
- 20. Signed functions
- 21. Sign conversion system functions
- 22. Arithmetic shift operators
- 23. Assignment width extension past 32 bits
- 24. Power operator
- 25. Attributes
- 26. Sized and typed parameter constants
- 27. Explicit in-line parameter redefinition
- 28. Fixed local parameters
- 29. Standard random number generator
- 30. Extended number of open files
- 31. Enhanced file I/O
- 32. String read and write system tasks
- 33. Enhanced invocation option testing
- 34. Enhanced conditional compilation
- 35. Source file and line compiler directive
- 36. Generate blocks
- 37. Configurations
- 38. On-detect pulse error propagation
- 39. Negative pulse detection
- 40. Enhanced input timing checks
- 41. Negative input timing constraints
- 42. Enhanced SDF file support
- 43. Extended VCD files
- 44. Enhanced PLA system tasks
- 45. Enhanced Verilog PLI support
- Appendix A: Verilog-2001 formal definition
- Appendix B: Verilog-2001 reserved words