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Test Resource Partitioning for System-on-a-Chip

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, su...

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Bibliographic Details
Main Authors: Iyengar, Vikram, Chandra, Anshuman (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 2002, 2002
Edition:1st ed. 2002
Series:Frontiers in Electronic Testing
Subjects:
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Electronic Circuits
Computer-aided Engineering
Electronic Circuits And Systems
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1. Test Resource Partitioning
  • 2. Test Access Mechanism Optimization
  • 3. Improved Test Bus Partitioning
  • 4. Test Wrapper And TAM Co-Optimization
  • 5. Test Scheduling
  • 6. Precedence, Preemption, And Power Constraints
  • 7. Test Data Compression Using Golomb Codes
  • 8. Frequency-Directed Run-Length (FDR) Codes
  • 9. TRP for Low-Power Scan Testing
  • 10. Conclusion
  • References

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