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140122 ||| eng |
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|a 9781461328216
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| 100 |
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|a Brayton, Robert K.
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| 245 |
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|a Logic Minimization Algorithms for VLSI Synthesis
|h Elektronische Ressource
|c by Robert K. Brayton, Gary D. Hachtel, C. McMullen, Alberto L. Sangiovanni-Vincentelli
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| 250 |
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|a 1st ed. 1984
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| 260 |
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|a New York, NY
|b Springer US
|c 1984, 1984
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| 300 |
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|a XII, 194 p
|b online resource
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| 505 |
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|a 1. Introduction -- 1.1 Design Styles for VLSI Systems -- 1.2 Automatic Logic Synthesis -- 1.3 PLA Implementation -- 1.4 History of Logic Minimization -- 1.5 ESPRESSO-II -- 1.6 Organization of the Book -- 2. Basic Definitions -- 2.1 Operations on Logic Functions -- 2.2 Algebraic Representation of a Logic Function -- 2.3 Cubes and Covers -- 3. Decomposition and Unate Functions -- 3.1 Cofactors and the Shannon Expansion -- 3.2 Merging -- 3.3 Unate Functions -- 3.4 The Choice of the Splitting Variable -- 3.5 Unate Complementation -- 3.6 SIMPLIFY -- 4. The ESPRESSO Minimization Loop and Algorithms -- 4.0 Introduction -- 4.1 Complementation -- 4.2 Tautology -- 4.3 Expand -- 4.4 Essential Primes -- 4.5 Irredundant Cover -- 4.6 Reduction -- 4.7 Lastgasp -- 4.8 Makesparse -- 4.9 Output Splitting -- 5. Multiple-Valued Minimization -- 6. Experimental Results -- 6.1 Analysis of Raw Data for ESPRESSO-IIAPL -- 6.2 Analysis of Algorithms -- 6.3 Optimality of ESPRESSO-II Results -- 7. Comparisons and Conclusions -- 7.1 Qualitative Evaluation of Algorithms of ESPRESSO-II -- 7.2 Comparison with ESPRESSO-IIC -- 7.3 Comparison of ESPRESSO-II with Other Programs -- 7.4 Other Applications of Logic Minimization -- 7.5 Directions for Future Research -- References
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| 653 |
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|a Computer-Aided Engineering (CAD, CAE) and Design
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| 653 |
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|a Electrical and Electronic Engineering
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| 653 |
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|a Electrical engineering
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| 653 |
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|a Computational Mathematics and Numerical Analysis
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| 653 |
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|a Mathematics / Data processing
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| 653 |
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|a Computer-aided engineering
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| 700 |
1 |
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|a Hachtel, Gary D.
|e [author]
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| 700 |
1 |
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|a McMullen, C.
|e [author]
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| 700 |
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|a Sangiovanni-Vincentelli, Alberto L.
|e [author]
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| 041 |
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7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 490 |
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|a The Springer International Series in Engineering and Computer Science
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| 028 |
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|a 10.1007/978-1-4613-2821-6
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| 856 |
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|u https://doi.org/10.1007/978-1-4613-2821-6?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
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|a 670.285
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| 520 |
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|a The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee
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