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140122 ||| eng |
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|a 9781461315599
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| 100 |
1 |
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|a Ping-Sheng Tseng
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| 245 |
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|a A Systolic Array Parallelizing Compiler
|h Elektronische Ressource
|c by Ping-Sheng Tseng
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| 250 |
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|a 1st ed. 1990
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| 260 |
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|a New York, NY
|b Springer US
|c 1990, 1990
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| 300 |
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|a XVIII, 130 p
|b online resource
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| 505 |
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|a 1 Introduction -- 2 Systolic array programming -- 2.1 The Warp machine -- 2.2 The W2 programming language -- 2.3 The AL programming language -- 2.4 Related work -- 3 Data relations -- 3.1 Linear data relations -- 3.2 Joint data compatibility classes -- 3.3 Scope of data compatibility classes -- 3.4 Summary -- 4 Loop Distribution -- 4.1 Intercell communication -- 4.2 The basic loop distribution scheme -- 4.3 Distributed loop parallelism -- 4.4 Optimization -- 4.5 Related work -- 5 Implementation -- 5.1 External interface -- 5.2 Compiling DO* loops -- 5.3 The ALIGN* statement -- 5.4 Parallel accumulation -- 5.5 Program debugging -- 6 Evaluation -- 6.1 Matrix computations -- 6.2 2D Fast Fourier Transform -- 6.3 Partial differential equation solvers -- 6.4 Summary -- 7 Conclusions -- A Linear data relations in Livermore Loops -- B Benchmark programs -- B.1 LU decomposition -- B.1.1 Single cell -- B.1.2 Multiple cells -- B.2 QR decomposition -- B.2.1 Single cell -- B.2.2 Multiple cells -- B.3 Singular value decomposition -- B.3.1 Single cell -- B.3.2 Multiple cell -- B.4 2D Fast Fourier Transform -- B.4.1 Single cell -- B.4.2 Multiple cell -- B.5 Partial differential equation solvers -- B.5.1 SOR -- B.5.2 Line SOR -- B.5.3 Two-color SOR.
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| 653 |
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|a Signal, Speech and Image Processing
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| 653 |
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|a Processor Architectures
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| 653 |
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|a Microprocessors
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| 653 |
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|a Signal processing
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| 653 |
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|a Computer architecture
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| 041 |
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7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 490 |
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|a The Springer International Series in Engineering and Computer Science
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| 028 |
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|a 10.1007/978-1-4613-1559-9
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| 856 |
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|u https://doi.org/10.1007/978-1-4613-1559-9?nosfx=y
|x Verlag
|3 Volltext
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|a 004.22
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| 520 |
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|a Widespread use of parallel processing will become a reality only if the process of porting applications to parallel computers can be largely automated. Usually it is straightforward for a user to determine how an application can be mapped onto a parallel machine; however, the actual development of parallel code, if done by hand, is typically difficult and time consuming. Parallelizing compilers, which can gen erate parallel code automatically, are therefore a key technology for parallel processing. In this book, Ping-Sheng Tseng describes a parallelizing compiler for systolic arrays, called AL. Although parallelizing compilers are quite common for shared-memory parallel machines, the AL compiler is one of the first working parallelizing compilers for distributed memory machines, of which systolic arrays are a special case. The AL compiler takes advantage of the fine grain and high bandwidth interprocessor communication capabilities in a systolic architecture to generate efficient parallel code. xii Foreword While capable of handling an important class of applications, AL is not intended to be a general-purpose parallelizing compiler
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