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140122 ||| eng |
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|a 9781461315377
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|a Dubois, Michel
|e [editor]
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| 245 |
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|a Cache and Interconnect Architectures in Multiprocessors
|h Elektronische Ressource
|c edited by Michel Dubois, Shreekant S. Thakkar
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| 250 |
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|a 1st ed. 1990
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| 260 |
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|a New York, NY
|b Springer US
|c 1990, 1990
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| 300 |
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|a XIV, 277 p
|b online resource
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| 505 |
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|a TLB Consistency and Virtual Caches -- The Cost of TLB Consistency -- Virtual-Address Caches in Multiprocessors -- Simulation and Performance Studies — Cache Coherence -- A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors -- Performance of Symmetry Multiprocessor System -- Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors -- Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols -- Performance of Parallel Loops using Alternate Cache Consistency Protocols on a Non-Bus Multiprocessor -- Predicting the Performance of Shared Multiprocessor Caches -- Cache Coherence Protocols -- The Cache Coherence Protocol of the Data Diffusion Machine -- SCI (Scalable Coherent Interface) Cache Coherence -- Interconnect Architectures -- Performance Evaluation of Wide Shared Bus Multiprocessors -- Crossbar-Multi-processor Architecture -- “CHESS” Multiprocessor—A Processor-Memory Grid for Parallel Programming -- Software Cache Coherence Schemes -- Software-directed Cache Management in Multiprocessors
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| 653 |
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|a Processor Architectures
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| 653 |
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|a Microprocessors
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| 653 |
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|a Computer architecture
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| 700 |
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|a Thakkar, Shreekant S.
|e [editor]
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| 041 |
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7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b SBA
|a Springer Book Archives -2004
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| 028 |
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|a 10.1007/978-1-4613-1537-7
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| 856 |
4 |
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|u https://doi.org/10.1007/978-1-4613-1537-7?nosfx=y
|x Verlag
|3 Volltext
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|a 004.22
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| 520 |
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|a Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop
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