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Advanced Low-Power Digital Circuit Techniques

Advanced Low-Power Digital Circuit Techniques presents several novel high performance digital circuit designs that emphasize low-power and low-voltage operation. These circuits represent a wide range of circuits that are used in state-of-the-art VLSI systems and hence serve as good examples for low-...

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Bibliographic Details
Main Authors: Elrabaa, Muhammad S., Abu-Khater, Issam S. (Author), Elmasry, Mohamed I. (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 1997, 1997
Edition:1st ed. 1997
Series:The Springer International Series in Engineering and Computer Science
Subjects:
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Electronic Circuits
Computer-aided Engineering
Electronic Circuits And Systems
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1 Low-Power VLSI Design
  • 1.1 Power Estimation and Evaluation for Digital VLSI Circuits
  • 1.2 Low-Power Impact on Process and Technology
  • 1.3 This Book
  • References
  • 2 Low-Power High-Performance Adders
  • 2.1 Introduction
  • 2.2 Architecture
  • 2.3 Circuit Design and Implementation
  • 2.4 Optimization Using Variable Block Size Combination
  • 2.5 Simulation Strategy
  • 2.6 Circuit performance
  • 2.7 Layout Strategy
  • 2.8 Experimental Results
  • 2.9 Summary
  • References
  • Low-Power High-Performance Multipliers
  • 3.1 Introduction
  • 3.2 Review of Parallel Multipliers
  • 3.3 Multiplier Architecture and Simulation Method
  • 3.4 Multiplier Cell
  • 3.5 Booth Encoder
  • 3.6 Add Cell
  • 3.7 CSA
  • 3.8 6-Bit Multiplier
  • 3.9 Summary
  • References
  • Low-Power Register File
  • 4.1 Introduction
  • 4.2 Architecture and Simulation Procedure
  • 4.3 Memory Cell Circuit
  • 4.4 Write Circuitry
  • 4.5 Read Circuitry
  • 4.6 Decoder Circuit
  • 4.7 32x32-bit Register File
  • 4.8 Summary
  • References
  • Low-Power Embedded Bicmos/ECL Srams
  • 5.1 Introduction
  • 5.2 16 Mb+ SRAMs Front-end Optimization
  • 5.3 The Novel W-ORing and Level-Translation Circuits
  • 5.4 The Novel Self-Resetting WL Decoder and Driver
  • 5.5 The Novel Latched Sense-Amplifier
  • 5.6 Chapter Summary
  • References
  • BICMOS On-Chip Drivers
  • 6.1 Introduction
  • 6.2 The Novel Full-Swing BiCMOS Circuit Technique
  • Performance Comparisons
  • 6.4 Design of the Feedback Circuitry
  • 6.5 Chapter Summary
  • References
  • Inter-Chip Low-Voltage-Swing Transceivers
  • 7.1 Introduction
  • 7.2 Low-Power ECL/CML Dynamic Circuit Techniques
  • 7.3 The Universal Transceiver (Receiver/Driver)
  • 7.4 Chapter Summary
  • References

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