Computer Aided Verification 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010, Proceedings

Corporate Author: SpringerLink (Online service)
Other Authors: Touili, Tayssir (Editor), Cook, Byron (Editor), Jackson, Paul (Editor)
Format: eBook
Language:English
Published: Berlin, Heidelberg Springer Berlin Heidelberg 2010, 2010
Edition:1st ed. 2010
Series:Theoretical Computer Science and General Issues
Subjects:
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
LEADER 04808nmm a2200445 u 4500
001 EB000384834
003 EBX01000000000000000237886
005 00000000000000.0
007 cr|||||||||||||||||||||
008 130626 ||| eng
020 |a 9783642142956 
100 1 |a Touili, Tayssir  |e [editor] 
245 0 0 |a Computer Aided Verification  |h Elektronische Ressource  |b 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010, Proceedings  |c edited by Tayssir Touili, Byron Cook, Paul Jackson 
250 |a 1st ed. 2010 
260 |a Berlin, Heidelberg  |b Springer Berlin Heidelberg  |c 2010, 2010 
300 |a XVI, 676 p. 169 illus  |b online resource 
505 0 |a A Compositional LTL Verifier -- Session 11. Tools -- A Model Checker for AADL -- PESSOA: A Tool for Embedded Controller Synthesis -- Session 12. Decision Procedures -- On Array Theory of Bounded Elements -- Quantifier Elimination by Lazy Model Enumeration -- Session 13. Concurrent Program Verification II -- Bounded Underapproximations -- Global Reachability in Bounded Phase Multi-stack Pushdown Systems -- Model-Checking Parameterized Concurrent Programs Using Linear Interfaces -- Dynamic Cutoff Detection in Parameterized Concurrent Programs -- Session 14. Tools -- PARAM: A Model Checker for Parametric Markov Models -- Gist: A Solver for Probabilistic Games -- A NuSMV Extension for Graded-CTL Model Checking 
505 0 |a Distributed and Symbolic Reachability -- libalf: The Automata Learning Framework -- Session 8. Synthesis -- Symbolic Bounded Synthesis -- Measuring and Synthesizing Systems in Probabilistic Environments -- Achieving Distributed Control through Model Checking -- Robustness in the Presence of Liveness -- RATSY – A New Requirements Analysis Tool with Synthesis -- Comfusy: A Tool for Complete Functional Synthesis -- Session 9. Concurrent Program Verification I -- Universal Causality Graphs: A Precise Happens-Before Model for Detecting Bugs in Concurrent Programs -- Automatically Proving Linearizability -- Model Checking of Linearizability of Concurrent List Implementations -- Local Verification of Global Invariants in Concurrent Programs --  
505 0 |a An Interpolating Model-Checker -- Breach, A Toolbox for Verification and Parameter Synthesis of Hybrid Systems -- Jtlv: A Framework for Developing Verification Algorithms -- Petruchio: From Dynamic Networks to Nets -- Session 4. Counter and Hybrid Systems Verification -- Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems -- Safety Verification for Probabilistic Hybrid Systems -- A Logical Product Approach to Zonotope Intersection -- Fast Acceleration of Ultimately Periodic Relations -- An Abstraction-Refinement Approach to Verification of Artificial Neural Networks -- Session 5. Memory Consistency -- Fences in Weak Memory Models -- Generating Litmus Tests for Contrasting Memory Consistency Models -- Session 6. Verification of Hardware and Low Level Code -- Directed Proof Generation for Machine Code -- Verifying Low-Level Implementations of High-Level Datatypes --  
505 0 |a From Theory to Practice? -- Memory Management in Concurrent Algorithms -- Invited Tutorials -- ABC: An Academic Industrial-Strength Verification Tool -- There’s Plenty of Room at the Bottom: Analyzing and Verifying Machine Code -- Constraint Solving for Program Verification: Theory and Practice by Example -- Session 1. Software Model Checking -- Invariant Synthesis for Programs Manipulating Lists with Unbounded Data -- Termination Analysis with Compositional Transition Invariants -- Lazy Annotation for Program Testing and Verification -- The Static Driver Verifier Research Platform -- Dsolve: Safety Verification via Liquid Types -- Contessa: Concurrency Testing Augmented with Symbolic Analysis -- Session 2. Model Checking and Automata -- Simulation Subsumption in Ramsey-Based Büchi Automata Universality and Inclusion Testing --  
653 |a Mathematical Logic and Formal Languages 
653 |a Computer Communication Networks 
653 |a Software engineering 
653 |a Computer science 
653 |a Artificial Intelligence 
653 |a Logics and Meanings of Programs 
653 |a Computer Communication Networks 
653 |a Artificial intelligence 
653 |a Logic design 
653 |a Programming Languages, Compilers, Interpreters 
653 |a Software Engineering 
700 1 |a Cook, Byron  |e [editor] 
700 1 |a Jackson, Paul  |e [editor] 
710 2 |a SpringerLink (Online service) 
041 0 7 |a eng  |2 ISO 639-2 
989 |b Springer  |a Springer eBooks 2005- 
490 0 |a Theoretical Computer Science and General Issues 
856 |u https://doi.org/10.1007/978-3-642-14295-6?nosfx=y  |x Verlag  |3 Volltext 
082 0 |a 005.1015113