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High Performance Embedded Architectures and Compilers 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings

This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were careful...

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Bibliographic Details
Other Authors: Patt, Yale N. (Editor), Foglia, Pierfrancesco (Editor), Duesterwald, Evelyn (Editor), Faraboschi, Paolo (Editor)
Format: eBook
Language:English
Published: Berlin, Heidelberg Springer Berlin Heidelberg 2010, 2010
Edition:1st ed. 2010
Series:Theoretical Computer Science and General Issues
Subjects:
Computer Communication Networks
Programming Techniques
Computer Programming
Computer Arithmetic And Logic Units
Computer Networks 
Input/output And Data Communications
Logic Design
Processor Architectures
Computer Input-output Equipment
Arithmetic And Logic Structures
Microprocessors
Computer Architecture
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
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250 |a 1st ed. 2010 
260 |a Berlin, Heidelberg  |b Springer Berlin Heidelberg  |c 2010, 2010 
300 |a XIII, 370 p  |b online resource 
505 0 |a Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions --  
505 0 |a DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders 
505 0 |a Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs --  
653 |a Computer Communication Networks 
653 |a Programming Techniques 
653 |a Computer programming 
653 |a Computer arithmetic and logic units 
653 |a Computer networks  
653 |a Input/Output and Data Communications 
653 |a Logic design 
653 |a Logic Design 
653 |a Processor Architectures 
653 |a Computer input-output equipment 
653 |a Arithmetic and Logic Structures 
653 |a Microprocessors 
653 |a Computer architecture 
700 1 |a Foglia, Pierfrancesco  |e [editor] 
700 1 |a Duesterwald, Evelyn  |e [editor] 
700 1 |a Faraboschi, Paolo  |e [editor] 
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520 |a This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators 

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