Transactions on High-Performance Embedded Architectures and Compilers II
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on...
| Other Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
Berlin, Heidelberg
Springer Berlin Heidelberg
2009, 2009
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| Edition: | 1st ed. 2009 |
| Series: | Transactions on High-Performance Embedded Architectures and Compilers
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| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
Table of Contents:
- Special Section on High-Performance Embedded Architectures and Compilers
- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
- Compiler-Assisted Memory Encryption for Embedded Processors
- Branch Predictor Warmup for Sampled Simulation through Branch History Matching
- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems
- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization
- Regular Papers
- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors
- Fetch Gating Control through Speculative Instruction Window Weighting
- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
- Linux Kernel Compaction through Cold Code Swapping
- Complexity Effective Bypass Networks
- A Context-Parameterized Model for Static Analysis of Execution Times
- Reexecution and Selective Reuse in Checkpoint Processors
- Compiler Support for Code Size Reduction Using a Queue-Based Processor
- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC
- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories