Full-Chip Nanometer Routing Techniques
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...
| Main Authors: | , , |
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| Format: | eBook |
| Language: | English |
| Published: |
Dordrecht
Springer Netherlands
2007, 2007
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| Edition: | 1st ed. 2007 |
| Series: | Analog Circuits and Signal Processing
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| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
Table of Contents:
- Routing Challenges for Nanometer Technology
- Multilevel Full-Chip Routing Considering Crosstalk And Performance
- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
- Multilevel Full-Chip Routing For The X-Based Architecture
- Concluding Remarks And Future Work