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Low-Power High-Level Synthesis for Nanoscale CMOS Circuits

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) r...

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Bibliographic Details
Main Authors: Mohanty, Saraju P., Ranganathan, Nagarajan (Author), Kougianos, Elias (Author), Patra, Priyardarsan (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 2008, 2008
Edition:1st ed. 2008
Subjects:
Electronics And Microelectronics, Instrumentation
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Computers
Computer Hardware
Electronic Circuits
Computer-aided Engineering
Electronics
Electronic Circuits And Systems
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • High-Level Synthesis Fundamentals
  • Power Modeling and Estimation at Transistor and Logic Gate Levels
  • Architectural Power Modeling and Estimation
  • Power Reduction Fundamentals
  • Energy or Average Power Reduction
  • Peak Power Reduction
  • Transient Power Reduction
  • Leakage Power Reduction
  • Conclusions and Future Direction

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