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SystemVerilog for Design Second Edition A Guide to Using SystemVerilog for Hardware Design and Modeling

This IEEE SystemVerilog standard adds new capabilities, clarifications, and changes to the Accellera 3.1 SystemVerilog upon which the first edition of this book was based. Significant updates and revisions in the new edition include: A new chapter showing how to use SystemVerilog packages with singl...

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Bibliographic Details
Main Authors: Sutherland, Stuart, Davidmann, Simon (Author), Flake, Peter (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 2006, 2006
Edition:2nd ed. 2006
Subjects:
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Computers
Computer Hardware
Electronic Circuits
Computer-aided Engineering
Electronic Circuits And Systems
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • to SystemVerilog
  • SystemVerilog Declaration Spaces
  • SystemVerilog Literal Values and Built-in Data Types
  • SystemVerilog User-Defined and Enumerated Types
  • SystemVerilog Arrays, Structures and Unions
  • SystemVerilog Procedural Blocks, Tasks and Functions
  • SystemVerilog Procedural Statements
  • Modeling Finite State Machines with SystemVerilog
  • SystemVerilog Design Hierarchy
  • SystemVerilog Interfaces
  • A Complete Design Modeled with SystemVerilog
  • Behavioral and Transaction Level Modeling

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