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Fault-Tolerance Techniques for SRAM-Based FPGAs

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technol...

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Bibliographic Details
Main Authors: Kastensmidt, Fernanda Lima, Reis, Ricardo (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 2006, 2006
Edition:1st ed. 2006
Series:Frontiers in Electronic Testing
Subjects:
Electronics And Microelectronics, Instrumentation
Hardware Performance And Reliability
Engineering Design
Electrical And Electronic Engineering
Electrical Engineering
Computers
Optical Materials
Logic Design
Electronics
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • Radiation Effects in Integrated Circuits
  • Single Event Upset (SEU) Mitigation Techniques
  • Architectural SEU Mitigation Techniques
  • High-Level SEU Mitigation Techniques
  • Triple Modular Redundancy (TMR) Robustness
  • Designing and Testing a TMR Micro-Controller
  • Reducing TMR Overheads: Part I
  • Reducing TMR Overheads: Part II
  • Final Remarks

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