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130626 ||| eng |
| 020 |
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|a 9780387263991
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| 100 |
1 |
|
|a Mishra, Prabhat
|
| 245 |
0 |
0 |
|a Functional Verification of Programmable Embedded Architectures
|h Elektronische Ressource
|b A Top-Down Approach
|c by Prabhat Mishra, Nikil D. Dutt
|
| 250 |
|
|
|a 1st ed. 2005
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| 260 |
|
|
|a New York, NY
|b Springer US
|c 2005, 2005
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| 300 |
|
|
|a XIX, 180 p
|b online resource
|
| 505 |
0 |
|
|a to Functional Verification -- Architecture Specification -- Architecture Specification -- Validation of Specification -- Top-Down Validation -- Executable Model Generation -- Design Validation -- Functional Test Generation -- Future Directions -- Conclusions
|
| 653 |
|
|
|a Electronic digital computers / Evaluation
|
| 653 |
|
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|a System Performance and Evaluation
|
| 653 |
|
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|a Computer-Aided Engineering (CAD, CAE) and Design
|
| 653 |
|
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|a Electrical and Electronic Engineering
|
| 653 |
|
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|a Electrical engineering
|
| 653 |
|
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|a Electronic circuits
|
| 653 |
|
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|a Computer-aided engineering
|
| 653 |
|
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|a Processor Architectures
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| 653 |
|
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|a Microprocessors
|
| 653 |
|
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|a Electronic Circuits and Systems
|
| 653 |
|
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|a Special Purpose and Application-Based Systems
|
| 653 |
|
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|a Computers, Special purpose
|
| 653 |
|
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|a Computer architecture
|
| 700 |
1 |
|
|a Dutt, Nikil D.
|e [author]
|
| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
|
| 989 |
|
|
|b Springer
|a Springer eBooks 2005-
|
| 028 |
5 |
0 |
|a 10.1007/b137514
|
| 856 |
4 |
0 |
|u https://doi.org/10.1007/b137514?nosfx=y
|x Verlag
|3 Volltext
|
| 082 |
0 |
|
|a 621.3815
|
| 520 |
|
|
|a Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems
|