1 Table of Contents: “...Introduction -- Efficient Hardware Acceleration for Embedded Machine Learning -- Memory Design...”

2 “... implementation paradigms of hardware accelerators, parallelism for heterogeneous multi- and many-core systems...”

3 “..., exploring the efficient hardware design of efficient machine learning accelerators, memory optimization...”

4 “..., exploring the efficient hardware design of efficient machine learning accelerators, memory optimization...”

5 “..., and accelerators that can form a SoC with processors...”