1 Table of Contents: “... and Future Work -- 2. What Makes an Asic Library Sign-Off -- 2.1. Introduction -- 2.2. Testing -- 2.3...”

2 Table of Contents: “..., and Modelware -- 1.4. The Other Languages and Formats -- 2. VHDL Tools -- 2.1. Introduction -- 2.2. Evaluating...”

3 Table of Contents: “... Language for Synthesise -- 1.4. A Book, an Outline -- 1.5. Synthesis Domain -- 1.6. Interests of Synthesis...”

4 Table of Contents: “... -- 2.1. Introduction -- 2.2. Overview of VHDL-A -- 2.3. A MOSFET Model -- 2.4. The VHDL-A Code for a...”

5 Table of Contents: “.... Introduction -- 2.2. The ADEPT Environment -- 2.3. Examples and Results -- 2.4. Conclusions -- 3. The Design...”

6 Table of Contents: “... -- 2.1. Introduction -- 2.2. Introduction to Object-Oriented Design -- 2.3. Possible Approaches -- 3...”

7 Table of Contents: “... Level Modeling And Hardware Architecture Trade-Off -- 2.1. Introduction -- 2.2. Modelling...”

8 Table of Contents: “... of Hardware for Embedded Systems -- 2.1. Introduction -- 2.2. Data Types -- 2.3. Modeling Hardware Components...”

9 Table of Contents: “...: Implementation of Methodology -- 2. A System-Level Performance Model and Method -- 2.1. Introduction -- 2.2...”

10 Table of Contents: “.... Mapping Expressions to Input Ports -- 21. The New Character Set -- 22. Identifier Generalization -- 23...”

11 Table of Contents: “... of Electronic Analog Systems -- 1.1. Introduction -- 1.2. Modeling Basic Analog Concepts -- 1.3. Network...”