On-Chip Networks
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High b...
| Main Authors: | , |
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| Format: | eBook |
| Language: | English |
| Published: |
Cham
Springer International Publishing
2009, 2009
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| Edition: | 1st ed. 2009 |
| Series: | Synthesis Lectures on Computer Architecture
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| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
| Summary: | With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions |
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| Physical Description: | IV, 141 p online resource |
| ISBN: | 9783031017254 |