Network-on-Chip Architecture, Optimization, and Design Explorations
Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (No...
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| Other Authors: | , , |
| Format: | eBook |
| Language: | English |
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IntechOpen
2022
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| Collection: | Directory of Open Access Books - Collection details see MPG.ReNa |
| Summary: | Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems. |
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| Item Description: | Creative Commons (cc), https://creativecommons.org/licenses/by/3.0/ |
| Physical Description: | 1 electronic resource (110 p.) |
| ISBN: | intechopen.91110 9781839681486 9781839681592 9781839681585 |