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ASIC Design and Synthesis RTL Design Using Verilog

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in...

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Bibliographic Details
Main Author: Taraate, Vaibbhav
Format: eBook
Language:English
Published: Singapore Springer Nature Singapore 2021, 2021
Edition:1st ed. 2021
Subjects:
Microprogramming 
Control Structures And Microprogramming
Electronic Circuits
Logic Design
Electronic Circuits And Systems
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • Chapter 1. Introduction
  • Chapter 2. Design using CMOS
  • Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL)
  • Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL)
  • Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL)
  • Chapter 6. ASIC design guidelines
  • Chapter 7. ASIC RTL Verification
  • Chapter 8. FSM using VHDL and synthesis
  • Chapter 9. ASIC design improvement techniques
  • Chapter 10. ASIC Synthesis using Synopsys DC
  • Chapter 11. Design for Testability
  • Chapter 12. Static timing analysis
  • Chapter 13. Multiple Clock domain designs
  • Chapter 14. Low power ASIC design
  • Chapter 15. ASIC Physical design

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