|
|
|
|
| LEADER |
02807nmm a2200433 u 4500 |
| 001 |
EB001897469 |
| 003 |
EBX01000000000000001060474 |
| 005 |
00000000000000.0 |
| 007 |
cr||||||||||||||||||||| |
| 008 |
200604 ||| eng |
| 020 |
|
|
|a 9783030432430
|
| 100 |
1 |
|
|a Lutsyk, Petro
|
| 245 |
0 |
0 |
|a A Pipelined Multi-Core Machine with Operating System Support
|h Elektronische Ressource
|b Hardware Implementation and Correctness Proof
|c by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul
|
| 250 |
|
|
|a 1st ed. 2020
|
| 260 |
|
|
|a Cham
|b Springer International Publishing
|c 2020, 2020
|
| 300 |
|
|
|a XV, 628 p. 1 illus
|b online resource
|
| 505 |
0 |
|
|a Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic
|
| 653 |
|
|
|a Microprogramming
|
| 653 |
|
|
|a Computer science
|
| 653 |
|
|
|a Programming Techniques
|
| 653 |
|
|
|a Computer programming
|
| 653 |
|
|
|a Logic in AI.
|
| 653 |
|
|
|a Computer networks
|
| 653 |
|
|
|a Computer Engineering and Networks
|
| 653 |
|
|
|a Control Structures and Microprogramming
|
| 653 |
|
|
|a Input/Output and Data Communications
|
| 653 |
|
|
|a Computer input-output equipment
|
| 653 |
|
|
|a Computer engineering
|
| 653 |
|
|
|a Theory of Computation
|
| 653 |
|
|
|a Logic programming
|
| 700 |
1 |
|
|a Oberhauser, Jonas
|e [author]
|
| 700 |
1 |
|
|a Paul, Wolfgang J.
|e [author]
|
| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
|
| 989 |
|
|
|b Springer
|a Springer eBooks 2005-
|
| 490 |
0 |
|
|a Theoretical Computer Science and General Issues
|
| 028 |
5 |
0 |
|a 10.1007/978-3-030-43243-0
|
| 856 |
4 |
0 |
|u https://doi.org/10.1007/978-3-030-43243-0?nosfx=y
|x Verlag
|3 Volltext
|
| 082 |
0 |
|
|a 005.11
|
| 520 |
|
|
|a This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk
|