Using Artificial Neural Networks for Analog Integrated Circuit Design Automation

This book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to...

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Main Authors: Rosa, João P. S., Guerra, Daniel J. D. (Author), Horta, Nuno C. G. (Author), Martins, Ricardo M. F. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: Cham Springer International Publishing 2020, 2020
Edition:1st ed. 2020
Series:SpringerBriefs in Applied Sciences and Technology
Subjects:
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Summary:This book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies.
Physical Description:XVIII, 101 p online resource
ISBN:9783030357436