%0 eBook
%M Solr-EB001884712
%E Goodrich, Michael T.
%E McGeoch, Catherine C.
%I Springer Berlin Heidelberg
%D 1999
%C Berlin, Heidelberg
%G English
%B Lecture Notes in Computer Science
%@ 9783540485186
%T Algorithm Engineering and Experimentation : International Workshop ALENEX'99 Baltimore, MD, USA, January 15-16, 1999, Selected Papers
%U https://doi.org/10.1007/3-540-48518-X?nosfx=y
%7 1st ed. 1999
%X Symmetric multiprocessors (SMPs) dominate the high-end server market and are currently the primary candidate for constructing large scale multiprocessor systems. Yet, the design of e cient parallel algorithms for this platform c- rently poses several challenges. The reason for this is that the rapid progress in microprocessor speed has left main memory access as the primary limitation to SMP performance. Since memory is the bottleneck, simply increasing the n- ber of processors will not necessarily yield better performance. Indeed, memory bus limitations typically limit the size of SMPs to 16 processors. This has at least twoimplicationsfor the algorithmdesigner. First, since there are relatively few processors availableon an SMP, any parallel algorithm must be competitive with its sequential counterpart with as little as one processor in order to be r- evant. Second, for the parallel algorithm to scale with the number of processors, it must be designed with careful attention to minimizing the number and type of main memory accesses. In this paper, we present a computational model for designing e cient al- rithms for symmetric multiprocessors. We then use this model to create e cient solutions to two widely di erent types of problems - linked list pre x com- tations and generalized sorting. Both problems are memory intensive, but in die rent ways. Whereas generalized sorting algorithms typically require a large numberofmemoryaccesses, they areusuallytocontiguousmemorylocations. By contrast, prex computation algorithms typically require a more modest qu- tity of memory accesses, but they are are usually to non-contiguous memory locations
%R 10.1007/3-540-48518-X