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Low-Noise Low-Power Design for Phase-Locked Loops Multi-Phase High-Performance Oscillators

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.  The capacitive...

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Bibliographic Details
Main Authors: Zhao, Feng, Dai, Fa Foster (Author)
Format: eBook
Language:English
Published: Cham Springer International Publishing 2015, 2015
Edition:1st ed. 2015
Subjects:
Electronics And Microelectronics, Instrumentation
Electronic Circuits
Signal, Speech And Image Processing
Electronics
Electronic Circuits And Systems
Signal Processing
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
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300 |a XIII, 96 p. 73 illus., 24 illus. in color  |b online resource 
505 0 |a Introduction -- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL -- A Wide-Band 0.13µm SiGe BiCMOS PLL for X-Band Radar -- Design and Analysis of QVCO with Different Coupling Techniques -- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique -- Conclusions 
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653 |a Electronic Circuits and Systems 
653 |a Signal processing 
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520 |a This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.  The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage.  Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.  

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