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141103 ||| eng |
| 020 |
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|a 9783319068381
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| 100 |
1 |
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|a Gong, Lingkan
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| 245 |
0 |
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|a Functional Verification of Dynamically Reconfigurable FPGA-based Systems
|h Elektronische Ressource
|c by Lingkan Gong, Oliver Diessel
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| 250 |
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|a 1st ed. 2015
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| 260 |
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|a Cham
|b Springer International Publishing
|c 2015, 2015
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| 300 |
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|a XXI, 216 p. 72 illus., 48 illus. in color
|b online resource
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| 505 |
0 |
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|a Introduction -- Verification Challenges -- Modeling Reconfiguration -- Getting Started with Verification -- Case Studies -- References Designs -- Conclusions.- Appendix A: Bugs Detected in Case Studies -- Appendix B: Inside the ReSim Library -- References
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Processor Architectures
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| 653 |
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|a Microprocessors
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| 653 |
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|a Electronic Circuits and Systems
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| 653 |
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|a Computer architecture
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| 700 |
1 |
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|a Diessel, Oliver
|e [author]
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| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b Springer
|a Springer eBooks 2005-
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| 028 |
5 |
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|a 10.1007/978-3-319-06838-1
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| 856 |
4 |
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|u https://doi.org/10.1007/978-3-319-06838-1?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 621.3815
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| 520 |
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|a This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them; Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects; Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described; Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, ModelSim simulator, Verilog/VHDL design language, etc. …)
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