High-Performance Digital VLSI Circuit Design

High-Performance Digital VLSI Circuit Design is the first book devoted entirely to the design of digital high-performance VLSI circuits. CMOS, BiCMOS and bipolar ciruits are covered in depth, including state-of-the-art circuit structures. Recent advances in both the computer and telecommunications i...

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Bibliographic Details
Main Authors: Gu, Richard X., Sharaf, Khaled M. (Author), Elmasry, Mohamed I. (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 1996, 1996
Edition:1st ed. 1996
Series:The Springer International Series in Engineering and Computer Science
Subjects:
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 5.2 CML and ECL Previous Delay Models
  • 5.3 New CML Propagation Delay Model
  • 5.4 Transient Analysis
  • 5.5 High-Current Effects
  • 5.6 Model Verification and Its Application in Circuit Optimization
  • 5.7 Model Limitations
  • 5.8 Chapter Summary
  • References
  • 6 Series-Gated Cml and Ecl Bipolar Circuits
  • 6.1 Introduction
  • 6.2 Two-level Series-gating CML and ECL Circuit Design
  • 6.3 Analysis and Optimization of Two-level Circuits
  • 6.4 Series-Gated CML and ECL Circuits
  • 6.5 Results and Model Verification
  • 6.6 Model Applications in Optimizing CML and ECL Series- Gated High-Speed Circuits
  • 6.7 Chapter Summary
  • References
  • 7 High-Performance Bicmos Circuit Structures
  • 7.1 Introduction
  • 7.2 ECL/CMOS Interface Circuits
  • 7.3 Dynamic ECL Reference Voltage (DRV) CMOS/ECL Interface Circuits
  • 7.4 BiCMOS Sense Amplifiers for SRAM
  • 7.5 Chapter Summary
  • References
  • 8 High-performance Cml, Ecl and Ntl Bicmos Circuits
  • 8.1 Introduction
  • 8.2 Low-Power Circuits and Systems
  • 8.3 BJT and MOS Series-Gated CML Circuit Techniques
  • 8.4 Performance of XOR, D-latch BJT and MOS Series-Gated Circuits
  • 8.5 Performance of CML D-Latch Comparator Circuits
  • 8.6 High-Performance ECL Circuit Techniques
  • 8.7 Active Load (Series Diode and Resistor)
  • 8.8 Active-Pull-Down Techniques
  • 8.9 Discussion and Assessment of Active-Pull-Down ECL Cir-cuit Techniques
  • 8.10 BiCMOS Active-Pull-Down ECL Circuit Technique
  • 8.11 Non-Threshold-Logic Circuits
  • 8.12 Conventional NTL Circuits
  • 8.13 APD-NTL Circuit Techniques
  • 8.14 APD-NTL Circuit Performance
  • 8.15 Applications
  • 8.16 Chapter Summary
  • References
  • 9 High-Performance System Applications
  • 9.1 Introduction
  • 9.2 Phase-Locked Loops
  • 9.3 Phase-Locked Loop Building Blocks
  • 9.4 Chapter Summary
  • References
  • A Appendix
  • B Appendix
  • 1 Introduction
  • 1.1 Comparisons Between Bipolar and MOS Transistors
  • 1.2 CMOS Digital Circuits
  • 1.3 Bipolar ECL Circuits
  • 1.4 BiCMOS Circuits
  • 1.5 Power-Delay Tradeoffs Between CMOS, Bipolar ECL and BiCMOS Circuits
  • 1.6 Book Organization
  • References
  • 2 Device Design Considerations
  • 2.1 Design Considerations for MOSFETs
  • 2.2 Design Considerations for Bipolar Transistors
  • 2.3 Cutoff Frequency
  • 2.4 BiCMOS Device Design Considerations
  • 2.5 BiCMOS Device Scaling
  • 2.6 Chapter Summary
  • References
  • 3 Device Modeling
  • 3.1 Modeling of the MOS Transistor
  • 3.2 Modeling of the Bipolar Transistor
  • 3.3 Chapter Summary
  • References
  • 4 Cmos High-Performance Circuits
  • 4.1 Static Digital CMOS Circuits
  • 4.2 Non-Pipelined Dynamic CMOS Circuits
  • 4.3 Pipelined Dynamic CMOS Circuits
  • 4.4 An All-N-Logic Single-Phase Pipelined Dynamic CMOS Logic
  • 4.5 Chapter Summary
  • References
  • 5 A Cml Propagation Delay Model
  • 5.1 Introduction