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VHDL: Hardware Description and Design

VHDL is a comprehensive language that allows a user to deal with design complexity. Design, and the data representing a design, are complex by the very nature of a modern digital system constructed from VLSI chips. VHDL is the first language to allow one to capture all the nuances of that complexity...

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Bibliographic Details
Main Authors: Lipsett, Roger, Schaefer, Carl F. (Author), Ussery, Cary (Author)
Format: eBook
Language:English
Published: New York, NY Springer US 1989, 1989
Edition:1st ed. 1989
Subjects:
Electrical And Electronic Engineering
Electrical Engineering
Computers
Computer Hardware
Electronic Circuits
Electronic Circuits And Systems
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1 — Introduction
  • Why VHDL
  • Terminology and Conventions
  • 2 — A Model of Hardware
  • A Model of Behavior
  • A Model of Time
  • A Model of Structure
  • 3 — Basics
  • Structure and Behavior
  • Data Types and Objects
  • Hooking Constructs Together
  • Major VHDL Constructs
  • Libraries
  • 4 — Data Types
  • Literals
  • Scalar Types
  • Composite Types
  • Subtypes
  • Attributes
  • Predefined Operators
  • 5 — Behavioral Description
  • Process Statements
  • Behavioral Modeling — Sequential View
  • Behavioral Modeling — Concurrent View
  • 6 — Structural Description
  • Basic Features of Structural Description
  • Regular Structures
  • Configuration Specifications
  • Default Values and Unconnected Ports
  • 7 — Large Scale Design
  • Managing Shared Designs
  • Visibility and the Analysis Context
  • Partitioning a Design
  • Sharing Data Within a Design
  • Specifying a Design Configuration
  • Mixing Structure and Behavior
  • 8 — A Complete Example
  • The Traffic Light Controller
  • Creating the Specification
  • Partitioning the Design
  • Starting the Implementation
  • Setting Up the PLA
  • 9 — Advanced Features
  • Overloading
  • Access Types
  • File Types and I/O
  • User-Defined Attributes
  • Signal-Related Attributes
  • Aliases
  • Association by Subelement
  • Guarded Assignment Statements
  • Disconnection Specifications
  • Null Transactions
  • 10 — VHDL in Use
  • A Device Controller
  • Setup and Hold Timing
  • A Neural Net
  • A Systolic Array Multiplier
  • Summary
  • Appendix A — Predefined Environment261
  • Reserved Words
  • Attributes
  • Type and Subtype Attributes
  • Array Attributes
  • Signal-Valued Attributes
  • Signal-Related Attributes
  • Packages
  • The Package STANDARD
  • The Package TEXTIO
  • >Appendix B — VHDL Syntax
  • >Appendix C — Suggested Reading
  • >Index

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